Integrated circuits often incorporate power devices designed to drive external loads. External loads may exhibit fault conditions, such as internal short circuits or open circuits, or impedance changes due to aging or component failure. Certain fault conditions may place electrical overstresses upon the integrated circuit which is driving the faulty load. For example, suppose an integrated circuit IC.sub.1 of FIG. 1 contains a series-pass element M.sub.1 which is connected between a low-impedance voltage source V.sub.in and a resistive load R.sub.L. Under normal operating conditions, the series-pass element M.sub.1 is either on or off, and in neither case does the integrated circuit dissipate large amounts of power. If M.sub.1 is on, there will be little voltage across it, and if it is off, then little current will flow through it. Consequently, thermal dissipation within the integrated circuit is limited to a value which is nondestructive. However, if the load should fail, and consequently exhibit a low resistance to the flow of current, a potentially destructive condition occurs within the series-pass element M.sub.1. Because the resistance of this element is now large when compared to that of the faulty load, the majority of the voltage drop is across M.sub.1, and large amounts of current flow. The junction temperature of the integrated circuit will rapidly rise, and unless the fault is quickly removed, the integrated circuit will be destroyed.
Prior-art implementations of integrated circuit power drivers were typically protected by means of current limiting. A typical current limiting technique involves the placement of a current sense element in series with the series pass element, thereby allowing the integrated circuit to sense the flow of current through this device. If an excessive current flow is detected, the series pass device is disabled, protecting the circuit. This technique has the disadvantage of requiring an external reset, since with the series-pass element disabled, the integrated circuit cannot tell if the fault has cleared. Since many loads may exhibit momentary short-circuiting, this technique is not widely applicable. Techniques have been developed which monitor the load and restore normal operation when the fault is cleared. Some of these techniques rely upon linear regulation of the series-pass element, while others rely upon digital switching of the pass element.
An typical prior-art linear current limit circuit is shown in FIG. 2. A NMOS power device M.sub.1 is driven by a CMOS inverter IV.sub.1 through a limiting resistor R.sub.1. The current flowing through the power device is sensed by R.sub.2. When the voltage across R.sub.2 is sufficient to turn NPN transistor Q.sub.1 on, this transistor will pull down upon the gate of M.sub.1. Because of the presence of resistor R.sub.1, the voltage at the gate of M.sub.1 will drop, causing the voltage V.sub.out to also drop. Because the load now has a lower voltage across it, the current drawn by the load will decrease. At some point, the negative feedback around Q.sub.1 will bring the circuit into equilibrium, with a constant current flowing through the load. The constant current limit is set by adjusting the value of resistor R.sub.2.
Linear current limit circuits are often supplemented by overtemperature sensors integrated onto the integrated circuit. Due to the relatively long thermal time constants of the silicon chip, a thermal sensor cannot be relied upon as a sole means of protection. By the time the thermal sensor has detected a fault, excess power may have resulted in localized overheating and device failure. However, a thermal sensor can be combined with a linear current limit to provide a superior protection scheme. In such a scheme, the linear current limit is deliberately set to a relatively high current value, one which would eventually lead to overheating of the integrated circuit.
Some integrated circuits have multiple output drivers, or channels. These integrated circuits often require that each channel have independent protection circuitry, so that if a load driven by one channel fails, the other channels will continue to operate normally. This has historically been implemented using independent current limits and thermal shutdown circuits for each channel; this solution requires careful layout of the thermal sense elements to minimize thermal interactions between different channels which are integrated onto a common substrate.
Unfortunately, a linear current limit circuit is often difficult to implement. The feedback loop containing Q.sub.1 is a high-gain loop, and will tend to oscillate unless it is stabilized. This circuit may also interfere with the driving capabilities of the inverter IV.sub.1, due to the resistance R.sub.1 which is incorporated as a part of the current limit circuit. In addition, independent thermal shutdown circuits become increasingly difficult as output specific on resistance, Rsp, also known as Rdson/Area becomes smaller. As die area shrinks, thermal interaction between channels increases and the integrity of independent thermal shutdown becomes questionable. For this reason, digital techniques for overcurrent protection have been developed. These digital solutions prevent an output in a fault condition from heating an adjacent output, causing an inadvertant shutdown of an output not exhibiting a fault condition. A typical digital current limiting technique uses pulse-width-modulation (PWM) to limit the power dissipation through the series-pass element.
FIG. 3 shows a typical digital current limit circuit. A current sense resistor R.sub.1 is inserted in the current path through power transistor M.sub.1. A voltage is developed across this resistor which is proportional to the current flowing through the power device. This voltage is sensed by comparator C.sub.1. When the voltage exceeds the voltage of the offset voltage source V.sub.ofs, the output of comparator C.sub.1 goes high, indicating an overcurrent condition. This sets flip-flop FF.sub.1, whose non-inverting output Q now goes high. T1 is a 2.sup.n Ripple Counter made up of n D Flip/Flops with an active low clear (CLRZ). When CLRZ is low, Qmsb of T1 is low. T1 is clocked by a constant frequency pulse train on input OSC. T2 is a 2.sup.x Ripple Counter made up of x D Flip/Flops with an active low preset (PREZ).
When PREZ is low, Qmsb of T2 is high. T2 is also clocked by the input OSC. When Q of FF1 goes high, T1 and T2 are enabled. The number of flip/flops in T2 and T1 is chosen such that x&gt;n. When T1 counts to 2.sup.n clocks of input OSC, a monostable, MONO1 is fired, clocking the input CLK of FF2. This causes the inverting output of FF2, QZ, to go low. The gate drive G1 to M1 is disabled, causing M1 to turn off. T2 continues to count OSC cycles, and when it reaches 2.sup.x counts, Qmsb of T2 goes low, clearing FF1 and FF2. This causes Q of FF1 to go low, and QZ of FF2 to go high. T1 and T2 are cleared and preset respectively, and gate drive, G1 is once again enabled. FIG. 4 represents a timing diagram demonstrating the duty cycle control of M1. If a short circuit condition is maintained, the output M1 is essentially turned off and on with a duty cycle equal to 2.sup.n /2.sup.x. By setting this oscillator's duty cycle to a small value (perhaps 1%), the power dissipation in M1 can be limited to a safe value. When the power transistor is on with a short circuit condition, a very large current will flow, limited only by the drive capacity of transistor M.sub.1 (for a MOS transistor, this means that current flow is limited only by the rdson of the transistor). This current would very quickly overheat the power device and destroy it, but the duty cycle control will disable the power transistor before overheating reaches a critical level. The low duty cycle then allows the power transistor time to cool down before another pulse of power is delivered. If a sufficiently small duty cycle is generated, this circuit can indefinitely operate in current limit without thermal runaway.
Duty-cycle control limits are not suitable for driving certain types of loads, such as incandescent lamps, which exhibit a time-dependent response. These loads require a large initial current in order to achieve a lower, steady-state operating current level. If the initial current level (called the inrush current) exceeds the current limit trip-point of a PWM current sense scheme, the driver will go into over-current detect mode and will begin to pulse-width-modulate the load. This may limit power flow into the load to a value insufficient for the load to heat up and achieve its lower, steady-state operating current level in the required time. In this case, the duty cycle output protection circuit prevents the integrated circuit from operating normally, which is clearly an undesirable circumstance.
What is needed is a more sophisticated form of duty-cycle control.